1. Field of the Invention
The present invention relates to an external clock synchronization semiconductor memory device, and more particularly to maintaining a signal output from a memory cell in an external clock synchronization semiconductor memory device.
2. Description of Related Art
A SRAM has been widely used as a volatile memory for storing data in semiconductor integrated circuits for various applications. A dual end configuration comprising two digit lines and a single end configuration in which a cell output is transmitted via a single digit line are known as SRAM configurations (for example, K. Takeda et al., “A read-Static-Noise-Margin-Free SRAM Cell for Low-Vdd and High-Speed Applications” Proc. 2005 IEEE Int. Solid-State Circuit Conf. pp. 478-479, 611). FIG. 6 is a block diagram illustrating schematically an internal clock synchronization SRAM 6 of a single end configuration. This is an example of the SRAM representing the background of the present invention. The internal clock synchronization SRAM 6 comprises a plurality of SRAM cells (in FIG. 6, three cells 61a-61c are shown by way of an example) and word lines 62a-62c for selecting one of the SRAM cells 61a-61c. Furthermore, the internal clock synchronization SRAM 6 comprises a digit line 63 for transmitting data signals that have been stored in the SRAM cells 61a-61c. An inverter serving as a sense amplifier 64 is connected to the output side of the digit line 63. Furthermore, a D latch 65 for fetching, outputting and maintaining the signals from the sense amplifier 64 is connected to the output of the sense amplifier 64.
A precharge circuit 66 is further connected to the digit line 63. The precharge circuit 66 is controlled by the output signal PC of a logical circuit 67. A delay circuit 68 is connected to one input of the OR logical circuit 67. Each internal circuit of the internal clock synchronization SRAM 6 is controlled by an internal clock signal ICL generated by an internal clock generation circuit 69 from a clock signal CLK. Here, a word signal on the word lines 62a-62c, a signal on the digit line 63, a sense amplifier output signal, a D latch output signal, and a D latch input signal are represented by WL, DT, DLDT, DO, and LACLK, respectively.
FIG. 7 is a timing chart illustrating the operation of the internal clock synchronization SRAM 6. In the example shown herein, data “0” (LOW signal) is outputted from a specific SRAM cell. In FIG. 7, each arrow symbol shows the relationship between one signal change and another signal change caused thereby. The same is true for all the timing charts explained hereinbelow. The internal clock generation circuit 69 generates an internal clock signal ICL with a pulse width less than that of an external clock signal CLK from which the internal clock signal is generated. The signals such as WL, PC, and LACLK are synchronized with the ICL. Because of the presence of the delay circuit 68, the PC falls with a delay with respect to the fall of the ICL. Here, the design is such that the HIGH width of the ICL is larger than the fall width of the DT.
The internal clock synchronization SRAM 6 is operated by an internal clock signal with a pulse width less than that of the external clock CLK. Therefore, the internal clock synchronization SRAM 6 is suitable for high-speed operation and is easily synchronization controlled. However, the problem associated therewith is that a circuit is required for generating the internal clock signal. Another problem is that the operation instability is increased in the course of high-speed operation.
By contrast, an external clock synchronization SRAM operating synchronously with an external clock signal is known. The external clock synchronization SRAM is inferior to the internal clock synchronization SRAM in terms of operation speed. However, it is generally superior to the internal clock synchronization SRAM in terms of circuit scale and operation stability. FIG. 8 is a block diagram illustrating schematically an external clock synchronization SRAM of a signal end configuration representing the background of the present invention. In FIG. 8, a external clock synchronization SRAM 8 comprises a plurality of banks. In FIG. 8, two banks 81a, 81b among them are shown by way of an example. Each bank 81a, 81b comprises a plurality of SRAM cells 811a-811d and a plurality of word lines 812a-812d connected to respective SRAM cells 811a-811d. Furthermore, each bank 81a, 81b comprises local digit lines 813a, 813b connected to each SRAM cell. A signal on the word lines 812a-812d is shown as WL and a signal on the local digit lines 813a, 813b is shown as DTL.
Inverters 814a, 814b are connected as sense amplifiers to respective output sides of the local digit lines 813a, 813b. The output of each inverter 814a, 814b is connected to the NMOS 815a, 815b. A global digit line 82 is connected to the NMOS outputs 815a, 815b of each bank. A signal on the global digit line 82 is shown as DTG. Furthermore, local precharge circuits 816a, 816b are connected to the output sides of the local digit lines 813a, 813b. The local precharge circuits 816a, 816b are controlled by control signals PCL.
An inverter serving as a global sense amplifier 83 is connected to the output side of the global digit line 82. The output of the global sense amplifier 83 is outputted as an output data signal DO to the outside via the inverter 85. A global precharge circuit 84 is connected to the output side of the global digit line 82. A PCG signal for controlling the precharge timing is inputted into the global precharge circuit 84. The global precharge circuit 84 turns to the ON state in response to the PCG signal and precharges the global digit line 82 to a global precharge potential (HIGH).
FIG. 9 is a timing chart illustrating the operation of the external clock synchronization SRAM 8. In the example shown herein, data “0” (LOW signal) is outputted from the selected SRAM cell. The PCL, WL, and PCG vary in response to the variation of the external clock signal CLK. If the DTL is caused to fall by the output from the selected SRAM cell, the DTG falls in response thereto. If the DTG falls, the output signal DO, which is at a precharge potential, changes from HIGH to LOW. If then the external clock signal CLK changes from HIGH to LOW, the PCL and PCG become LOW and the DTL and DTG are precharged to HIGH. Similarly, the output signal DO also changes to the precharge potential HIGH.
In FIG. 9, the holding time of the output signal is denoted by tOH. As follows from the explanation provided hereinabove, in the configuration of the external clock synchronization SRAM 8, the global precharge circuit 84 is switched ON/OFF at almost the same timing with the external clock signal CLK. For this reason, if the external clock signal CLK falls, the global precharge circuit 84 turns to the ON state and precharges the global digit line 12 to HIGH. Furthermore, the change in the output of the global precharge circuit 84 is represented by the change in the output signal DO. For this reason, despite the fact that a certain time essentially remains before the next data signal output is produced, the global precharge circuit 84 becomes ON in response to the fall of the external clock signal CLK. As a result, the output signal DO changes from LOW to HIGH at an early timing.